The present disclosure relates generally to semiconductor manufacturing. Specifically, the present disclosure relates to a semiconductor device having a composite wafer structure and a method of fabricating the same.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the mainstream course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size (e.g., the smallest component that can be created using a fabrication process) has decreased. However, this mainstream evolution needs to follow the Moore's rule by a huge investment in facility establishment. Therefore, it has been a study topic that using current semiconductor technology develops more valuable ICs product. CMOS MEMS happens to be a good candidate for that trend.
CMOS microelectromechanical systems (MEMS) devices are very small electro-mechanical systems incorporated into CMOS semiconductor IC circuits. One example of a MEMS device is a micro-inertial sensor. Traditional CMOS MEMS utilizes the back-end material like inter-metal-dielectrics (IMD) and metal layers as the inertial sensor material for spring and proof-mass. As a complex multi-layers design, the mechanical structure displays a unstable stress control and temperature instability. Further more, the MEMS structure utilizing the back-end material will occupy a part of CMOS circuit area that will increase the die size and cost. Besides the ICs and MEMS devices fabrication, traditional ICs dicing and packaging technology can't fully apply to MEMS as its floating mechanical structure (usually a proof mass with some supporting springs) will be damaged during the process. It is therefore another topic for CMOS MEMS to protect the device with a wafer-level scheme before it is sent to the post-end test and package process. Traditional packaging of MEMS devices use wire bonding and injection molding to protect a bonding area of the device. This type of packaging creates a relatively large overall size. For example, a common ratio for traditional device size before packaging and after packaging may be in a range of approximately 4-20 times the original device size, depending on the applied technology. Additionally, these devices are generally processed (e.g., to provide bonding wire connectors) one-by-one, which is time consuming and expensive.
However, today's mobile devices provide more and more functions, which in turn, requires more components, where the components need to be smaller and smaller. In addition, larger packaging requires more material to fabricate the packaging and therefore weighs more. All of this, adds to increased costs for the device in manufacturing, handling and shipping. Therefore, to solve above mentioned issues, what is needed is an innovative composite wafer semiconductor device, such as a MEMS device, and a method of fabrication.